HDLWorks Ease 9.6 R2 – Advanced HDL Development Environment

HDLWorks Ease 9.6 R2 is a specialized Integrated Development Environment (IDE) designed for hardware description languages (HDLs), focusing on VHDL, Verilog, and SystemVerilog. Developed for digital design engineers, it serves critical roles in FPGA development, ASIC design, and embedded systems across industries such as aerospace and defense. This software provides a robust platform for creating, simulating, and verifying complex digital circuits.

Comprehensive HDL Development for VHDL, Verilog, and SystemVerilog

HDLWorks Ease offers a complete solution for hardware description language development, meticulously supporting VHDL, Verilog, and SystemVerilog. Its application spans critical sectors including FPGA and ASIC design, embedded systems, and academic research in digital circuit design. The environment is engineered to enhance productivity and accuracy for professionals working on everything from intricate embedded logic to safety-critical systems found in aerospace applications.

Intelligent Coding and Syntax-Aware Editing

This IDE provides advanced language-aware editing capabilities crucial for complex HDL projects. Key features include:

  • Comprehensive syntax highlighting for VHDL (1987-2019 standards), Verilog (1995-2005 standards), and SystemVerilog.
  • Code folding and intelligent indentation to improve code readability and organization.
  • Smart code completion suggestions that reduce manual typing and minimize errors.
  • Advanced navigation tools such as call trees, direct cross-referencing, and symbol inspection for quick access to design elements.

Simulation and Verification Integration

HDLWorks Ease facilitates efficient hardware verification by integrating seamlessly with industry-standard simulation and verification tools. It supports a wide range of functionalities essential for design validation:

  • Direct integration with popular simulators including ModelSim, Questa, VCS, and Riviera-PRO.
  • Tools for generating stimulus and creating robust testbenches, supporting methodologies like OSVVM, UVVM, and VUnit.
  • Assertion-based verification capabilities, including support for Property Specification Language (PSL) and SystemVerilog Assertions (SVA).
  • Features for collecting code coverage data to ensure thorough verification.
  • An integrated waveform viewer for analyzing simulation results.

Project Management and Design Visualization

Managing complex multi-language hardware projects is streamlined with HDLWorks Ease’s robust project management and visualization features. Users benefit from:

  • Flexible project configuration supporting multiple HDLs simultaneously.
  • Automatic tracking of design dependencies to ensure accurate build processes.
  • Build automation through customizable scripting, leveraging Tcl and Python interfaces.
  • Integrated design visualization tools, including RTL schematics, state machine diagrams, and call graphs, to offer graphical insights into the design structure.
  • Capabilities for generating automatic design documentation, saving significant time for project reporting.

Collaboration, Customization, and Automation Features

To support modern engineering workflows, HDLWorks Ease incorporates features for team collaboration, extensive customization, and design automation. It enables:

  • Seamless integration with version control systems like Git, SVN, and Perforce for team collaboration and source code management.
  • Sharing of project configurations and code reviews to enhance team productivity.
  • Enforcement of coding standards through configurable linting rules.
  • Macro recording and scripting support using Tcl and Python for automating repetitive tasks and custom workflows.
  • The ability to submit simulation jobs remotely, including support for High-Performance Computing (HPC) clusters and cloud environments.

What’s New in HDLWorks Ease 9.6 R2

Version 9.6 R2 introduces several key enhancements aimed at improving the developer experience and design quality:

  • Significantly enhanced SystemVerilog support, including advanced constructs like classes and covergroups.
  • Introduction of live linting that provides real-time feedback on coding style and potential errors, with customizable rule sets.
  • An integrated diff viewer for comparing design versions directly within the IDE, streamlining code reviews and merge processes.
  • Updates to the coverage dashboard, providing a consolidated view of verification progress.
  • An improved waveform viewer interface with enhanced usability and performance.
  • Expanded support for HPC and cloud-based remote simulation job submissions for scalable verification.
  • General UI/UX refinements that contribute to a smoother and more intuitive user experience.

Frequently Asked Questions

What hardware description languages does HDLWorks Ease support?

HDLWorks Ease supports VHDL, covering standards from 1987 up to 2019, along with Verilog (1995-2005 standards) and SystemVerilog. The IDE features dedicated language-aware editing tools, ensuring precise syntax and semantic support for each of these critical hardware description languages.

Can HDLWorks Ease integrate with simulation and verification tools?

Yes, HDLWorks Ease integrates with key industry-standard simulators like ModelSim, Questa, VCS, and Riviera-PRO. It also broadens verification capabilities through support for frameworks such as OSVVM, UVVM, and VUnit, which greatly aids in testbench generation and comprehensive coverage-driven verification methodologies.

What new features does version 9.6 R2 of HDLWorks Ease introduce?

Version 9.6 R2 significantly enhances SystemVerilog support, including modern constructs like classes and covergroups. It also introduces live linting with customizable rules for real-time feedback, a version control diff viewer for efficient code comparison, a unified coverage dashboard, an updated waveform viewer interface, and new support for remote simulation job submissions to HPC and cloud platforms.