Siemens Questa One SFV

 

Siemens Questa One SFV (Static Formal Verification) 2026.1 is a breakthrough formal verification platform that delivers 20 stimulus-free analyses in a single product, eliminating traditional adoption hurdles of formal property checking. Version 2026.1 continues Siemens’ legacy of EDA innovation, offering scalable performance for efficient analysis, full design utilization, and novel, synergistic solutions for formal verification closure. Whether verifying high-assurance security properties, proving arithmetic assertion exhaustively, or checking connectivity and reset without testbench creation, Questa One SFV provides the breadth, depth, and automation that modern SoC and ASIC verification teams demand.

???? Primary Users

This professional formal verification software is designed for:

  • Formal Verification & Design Engineers proving design correctness without exhaustive simulation.

  • ASIC, FPGA & SoC Design Teams verifying complex designs from block-level to full-chip integration.

  • Automotive & Safety-Critical Designers achieving ISO 26262 ASIL D compliance through formal analysis.

  • Security Engineers verifying hardware security properties and information flow.

  • Verification & Methodology Leads augmenting simulation and emulation with static formal proof.

 

⚡ Key Features & Capabilities

???? 20+ Stimulus‑Free Analyses (One Product)

Analysis Category Specific Analyses
Connectivity & Integration Unconnected port/wire, constant driver, multiple driver
Clock & Reset Clock domain crossing (CDC) formal, reset domain crossing (RDC), glitch detection
Sequential Equivalence Sequential equivalence checking (SEC), retiming verification
Data Integrity X‑propagation, non‑determinism, data corruption
Structural Sanity Dead code, combinatorial loops, latch inference, fan‑out analysis
Low Power (UPF) Level shifter, isolation, power switch, retention (formal)
Arithmetic & Control Integer overflow, FSM reachability, assertion proving

⚡ Scalable Performance

Multi-Engine Architecture:

  • SAT / SMT (Bit‑Vector) solvers, BDD’s, model checking (explicit + symbolic)

  • Parallel solving: automatic decomposition of property set

Automatic Abstraction:

  • Sequential, cutpoint, and data-path reduction

  • Black-boxing (non-critical, previously proven)

Large Design Handling:

  • Hierarchical verification (proved block integrated as black box with constraints)

  • Assumption / guarantee (preconditions for deep sequential loops, memory)

???? Full Design Utilization (Simple Adoption)

Push‑Button Formal:

  • Zero property coding for structural and sanity checks

  • GUI‑driven or batch (open to all design / verification engineers)

Proven Correctness Guarantee:

  • Exhaustive proof (k‑induction, SAT reachability)

  • Counterexample traces (waveform, transition trace, state capture)

FPGA & ASIC Ready:

  • Full SystemVerilog / VHDL support (RTL, netlist, post‑synth)

  • Formal models for third‑party IP

???? Synergistic Integration with Other Nova™ Tools

Questa One SFV 2026.1 is part of Questa Nova line (formerly OneSpin) – synergy across formal engines:

  • Questa One CDC 360™ – formal CDC + RDC + glitch

  • Questa One X‑Prop 360™ – non‑determinism (X) handling

  • Questa One EC 360™ – sequential equivalence

  • Questa Connectivity Assistant – integration sanity, pin‑to‑pin checks

✅ Safety & Security (ISO 26262, Common Criteria, DO‑254)

Safety‑Critical Qualification:

  • ISO 26262 ASIL D and IEC 61508 SIL 3 certified (TÜV SÜD)

  • DO‑254 (avionics) tool qualification package available

Hardware Security Verification:

  • Information flow (non‑interference, covert channels)

  • Formal security properties: confidentiality, integrity, availability (CIA)

???? Productivity & Debug

Visualizer™ Integration:

  • Debug counterexample traces in Questa Visualizer (waveform, schematic, source)

  • Property coverage analysis after proof (unreachable states)

Automatic Property Generation:

  • From design intent (clock/reset, connectivity, wishbone/AMBA protocol)

  • From user‑defined templates (PSL/SVA)

Performance Reports & Bottleneck Analysis:

  • Property proving difficulty (resource usage, solver time)

  • Abstraction guidance recommendations