Aldec Riviera-PRO 2026.06 – The Next-Generation Functional Verification Platform for Advanced FPGA and SoC Design

Aldec Riviera-PRO is a flagship functional verification platform for engineers creating cutting-edge FPGA and SoC devices. It addresses the increasing complexity of modern hardware design by combining a high-performance simulation engine with advanced debugging capabilities and support for the latest language and verification library standards .

The 2026 release significantly enhances the platform’s capabilities, positioning it as a comprehensive solution for the entire verification lifecycle. A key addition in this version is the AI Assistant, a chatbot designed to help users create designs and assist with HDL (Hardware Description Language) code authoring, directly accessible from within the HDL Editor . This release also builds on the technology introduced in early 2026, which saw Riviera-PRO integrate with Aldec’s Hardware Visibility-based Debugging (HVD) technology for emulation, enabling seamless transition from simulation to hardware emulation . The platform is available for both Windows and Linux operating systems

Primary Users

Aldec Riviera-PRO 2026 is designed for hardware design and verification engineers who are developing complex FPGAs, SoCs, and ASICs. It serves professionals who need to:

  • Verify complex digital designs at the Register Transfer Level (RTL) using VHDL, Verilog, SystemVerilog, and SystemC .

  • Build and debug advanced testbenches based on the Universal Verification Methodology (UVM) .

  • Achieve high regression throughput for large-scale projects with an industry-leading simulation engine .

  • Perform comprehensive debugging at different levels of abstraction with a suite of advanced visual tools .

  • Ensure robust verification closure through metric-driven analysis using code and functional coverage.

Key Features & Capabilities

High-Performance Simulation Engine

Riviera-PRO is built on a powerful simulation engine that uses extensive optimization algorithms to deliver the highest performance for VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations . This industry-leading capacity and performance ensure high regression throughput for developing the most complex systems . The engine supports the latest verification libraries, including the Universal Verification Methodology (UVM), as well as VHDL verification libraries like OSVVM and UVVM .

Advanced Debugging Capabilities

Riviera-PRO provides a robust, integrated multi-language debug environment that automates time-consuming design analysis and enables quick bug fixing . The platform offers a suite of built-in debugging tools, including:

  • Waveform Viewer: Features include bookmarking, delta cycle analysis, dataset comparison, virtual grouping, and cross-probing for advanced signal analysis .

  • Dataflow Window: Visualizes the connectivity of a design through source code or a graphical display, aiding in tracing signals .

  • UVM Toolbox: Includes dedicated windows like UVM Graph, UVM Hierarchy, and UVM Configuration for visual mapping and debugging of UVM class libraries and their TLM (Transaction Level Modeling) connections .

  • Xtrace and Dataflow: An integrated tool that creates a report of unknown values (X, U, etc.) in a simulated model and can cross-probe with the Dataflow window to locate the source of these values .

  • Plot and Image Viewer: Provides graphical representation of data sets and visualization of images stored in memory-like simulation objects, offering powerful alternatives to traditional alphanumeric debugging .

  • Transaction Debugging: Includes tools for tracing and visualizing UVM and SystemVerilog transactions .

Assertion-Based Verification and Coverage

The platform offers comprehensive support for Assertion-Based Verification (ABV) using SystemVerilog Assertions (SVA) and Property Specification Language (PSL) . This increases design observability and decreases debug time . For verification closure, Riviera-PRO includes advanced Code and Functional Coverage capabilities and a coverage analysis tool for fast, metric-based verification . The flow is further streamlined by the ability to link user-defined test plans with the coverage database .

Hardware-Visibility Debugging (HVD) for Emulation

A significant feature introduced in the 2026 release cycle is the integration with Aldec’s HVD technology for hardware emulation. The HVD technology allows for the efficient transfer of data directly from an FPGA-based emulator to the Riviera-PRO simulation database, providing 100% signal visibility. This approach preserves original signal names and hierarchy paths and eliminates the need for unnecessary database conversion steps .

What’s New in Aldec Riviera-PRO 2026

The 2026 release introduces the AI Assistant, a new chatbot designed to help users create Riviera-PRO designs and assist with HDL code authoring. The AI Assistant integrates with a variety of AI service platforms and can be invoked directly from within the HDL Editor .

Other recent enhancements include advanced waveform operations such as bookmarks with comments, delta cycle analysis for debugging race conditions, and virtual grouping of signals in the Waveform Viewer, as well as the ability to compare simulation datasets directly in the GUI . A significant update from early 2026 also integrated Riviera-PRO with Aldec’s Hardware Visibility-based Debugging (HVD) technology, creating a seamless co-emulation debugging environment for hardware designers